At 08:53 AM 4/29/98 -0400, Andy Kunz wrote:
>>private. Heck, though we have never met I feel like I've known you for
>>around 3 years ;-)
>
>Same here.  Now I find one of our customers in named Tom Handley.  You
>don't work for a TV network in NYC, do you?

   Andy, that's a surprise! Our family sailed to Oregon from England in the
early 1800's and stayed in the Northwest.

>>   As with any PLD/CPLD/FPGA design there are a lot of trade-offs to be
>Er, uh, I only know how to make address decoders right now.  I was reading
>through the Cypress stuff, and was pretty much blown away.  A lot of
>studying to do.  When I was getting out of college, PAL's were just
>becoming available commercially!

   Like other vendors, Lattice's CPLDs are based on a common block, GLB in
this case. It's easy to learn. The Synario software includes a variety of
macros that simplify things. There are macros for counters, decoders,
mux/demux, registers/latches, a variety of arithmetic functions, etc. You
can use these at the schematic level with very little knowledge of the chip.
In the design you mentioned earlier, you can put that down in a few mins not
counting simulation. If you have experience with ABEL, you just add those as
function blocks for the schematic editor. You can take existing ABEL PLD
designs for 22V10s etc, and use them as-is.

>>own host ISP download software. This version is restricted to their 44-pin
>>CPLD devices (1016/E and 2032) but it is very powerful. Other than the
>
>Guess I have to pay for software for the chip I need, then?

   Andy the above devices are 64 and 32 macrocell devices with 32 I/Os,
4 inputs, and clock inputs. Larger devices require the full package which
costs up into the $$$$ range... You can still do a lot with the smaller
devices. In that one design I mentioned earlier, there's a 51-Bit shift
register and a 24-Bit coparator with individual enables. In another chip
I eliminated around 20 74x-family parts.

   - Tom