> From: Andy Kunz <mtdesign@FAST.NET>
> Jnls: PICLIST@MITVMA.MIT.EDU
> Rel`: Programmable Logic Questions
> D`r`: 27 `opek  1998 c. 22:45
>
> Has anybody out there done anything like the following with a single PLD,
> or two PLDs?
>
> Inputs:
>         Clock
>         Data
>         Output_Enable
>         Count
>         Reset
>
> Outputs:
>         16-bit counter output (increments on Count pin state change), and
reset to
> 0x0000 or 0xFFFF when pin Reset is put into a certain state.
>         16-bit shift-register output (from Clock/Data transitions)
>         NOTE:  All Outputs are Hi-Z or logic depending on state of
Output_Enable
>
> At the current time, it doesn't matter to me if the thing is edge- or
> level-triggered on the Clock, Count, and Reset pins.  The Clock/Data
forms
> a serial interface along the lines of SPI or such.

I do the same with Altera MAX7032 (7064). It is very easy to design such
PLD structure in MAX+Plus and programm the chip with ByteBlaster.

Alex Torres, Kharkov, Ukraine (exUSSR)
altor@geocities.com
2:461/28 FidoNet
http://www.geocities.com/SiliconValley/Lab/6311