Has anybody out there done anything like the following with a single PLD,
or two PLDs?

Inputs:
        Clock
        Data
        Output_Enable
        Count
        Reset

Outputs:
        16-bit counter output (increments on Count pin state change), and reset
to
0x0000 or 0xFFFF when pin Reset is put into a certain state.
        16-bit shift-register output (from Clock/Data transitions)
        NOTE:  All Outputs are Hi-Z or logic depending on state of Output_Enable

At the current time, it doesn't matter to me if the thing is edge- or
level-triggered on the Clock, Count, and Reset pins.  The Clock/Data forms
a serial interface along the lines of SPI or such.

If you've done this or have any related questions, please contact me
PRIVATE at mtdesign@fast.net or montana@fast.net

I'm interested in knowing what it takes (ie, which vendor, type chip, mode,
etc.), or paying someone who has done it to be able to use it.  I'm just
getting started in more complex PLD's and this seemed like a good place to
ask.  My experience with them to date has been to make address-bus
decoders, basically to make multiple 74-series parts into one chip.

Oh, yes, the obligatory PIC relationship:  It will used to program an
external memory for a PIC17.

Thanks.

Andy

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Andy Kunz - Statistical Research, Inc. - Westfield, New Jersey USA
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