if you have a chip that generates 391KHz to 100MHz you could multiplex between the direct osc. output and the output of a div-by-10 counter and a div-by-100 counter, with multiplexing control done by the pic. the multiplexing / clock dividing probably would fit into a 16v8 or 22v10 PAL (from Lattice, AMD, etc.), if space is a concern. Jason Sachs Electrical Engineer Deka Research & Development 340 Commercial Street Manchester, NH 03101 (603) 669 5139 x327 > -----Original Message----- > From: Frank Mckenney [SMTP:rrs0059@IBM.NET] > Sent: Friday, April 24, 1998 12:12 PM > To: PICLIST@MITVMA.MIT.EDU > Subject: Re: SquareWave > > Peter Schultz write: > > I am facing a big challenge and before I will go ahead I would like > to > > ask anybody who has a good idea. > > The solution not need to be cost effective. > > I need to generate square wave with close to 50% duty cycle, > > but quartz precision. > > The frequencies are : 400Hz - 4KHz 10Hz steps > > 4KHz -- 40KHz 100Hz steps > > 40KHz -- 400KHz 1000Hz steps > > 400KHz -- 4MHz 10000Hz steps > > Peter, > > You might want to take a look at the specifications for the Cypress > ICD2053B Programmable Clock Generator chip that was mentioned here a > few > days ago. Two-wire serial interface, tristate output, 8-pin package. > > http://www.cypress.com/products/timi/icd2053b.html > > The "down side" is the it will only cover the last part of your > desired > range, since it is limited to [391KHz - 100MHz]. However, Cypress (or > another manufacturer) may have a similar chip designed for > lower-frequency > operation. > > Hope this helps get thigns started... > > > Frank McKenney / OS/2 Advisor (OS2BBS) > McKenney Associates / Richmond, Virginia / (804) 320-4887 > Internet: rrs0059@ibm.net / TalkLink: WZ01123