>
> >Isn't there a chip out there that will control regular, PC 72-pin RAM
> >for me?  You know, handle the refresh and chip muxing?
>
> Umm, a PIC chip maybe?  Oh wait, too complicated.  It can be done though.
>  You'd connect some of the 32 data lines in parallel so the SIMM acts
> like 2 or 4 "narrower" memories of 16 or 8 bits.  Then use decoders (or
> extra PIC pins) to CAS only one or two of the 4 banks in the SIMM at once
> so the data doesn't conflict.   The PIC would still need to supply 9 or
> 10 bits of multiplexed address though.
>
> If you only need 2 MB and cost isn't a problem, use 4x 512 Kx8 SRAMs.
> Control the SRAM address with a counter (e.g. 2x 74HC4040 gives a 24 bit
> binary count, enough to address 16M locations).  Some of the counter bits
> (traditionally the higher-order ones) would be decoded to the chip select
> pins on the SRAMs so only one chip (for 8-bit bus) or pair of chips (for
> 16-bit bus) is active at a time.
>
Hmmm, this is a intrigueing suggestion.  So, by using your counter
chip, I can use regular SIMM's and only use 8 I/O lines?  Or are you
talking SRAM chips?  I'd like to be able to use a regular SIMM or
DIMM.

> I assume from the other post that the device has 2 modes of operation:
> "acquire" (ADC -> RAM) and "download" (RAM -> RS232) and that both
> operations don't have to happen at the same time.  So a simple address
> counter is ideal as a single PIC pin can reset it to zero at the start of
> each mode.  Another PIC pin would advance the count after each read or
> write.  The highest address in use would be stored in PIC RAM and an
> internal counter in the PIC would track the external count to tell when
> all data has been collected or sent.
>
This would work just fine.

> The data lines of the RAM would just connect directly to the data lines I
> assume already exist from the ADC(s) to the PIC, so no more pins would be
> needed for data.  The output-enables on each deevice would control the
> direction of data on the 8 or 16-bit bus.  I'd use an 8-bit bus if the
> ADCs allow it (have a "byte select" or dual output enables to send only 8
> bits at a time) since the speed is so low there's no advantage to a wider
> bus.  This will free up 8 PIC pins.  The data bus doesn't even have to be
> connected to the PIC at all except to read for RS-232, a parallel->serial
> shift register could be connected to shift the data in on one pin.  With
> a 40-pin PIC, such measures shouldn't be needed.
>
Yeah, that sounds good.

> Running two or more ADCs would be no problem, just connect them to the
> data bus and run the chip selects individually back to the PIC.  The PIC
> software would read and store one ADC, then select the other one, read
> and store it.  The readings would end up interleaved in the RAM.  If
> you're really short on PIC pins, the low order RAM address from the
> counter could even be decoded to select an ADC.  But then it wouldn't be
> possible to do things like sample only one ADC and fit twice as many
> samples in RAM.
>
>
I don't think so, what you described above should leave enough I/O's
free...

This is a really good e-mail.  I have a couple of questions about it
though...

1.  What part's are you referring to me using with the counter chip?
(part no, brand, etc..)

2.  How will I keep the SRAM refreshed?  Or do I not need to worry
abou that?

Thanks so much for your award-winning reply!