At 09:06 AM 3/27/98 -0300, Alexandre Guimaraes wrote:
>    Have you taken a look at Atmel's 40k series ? They have some high speed
>Sram inside the Fpga. It might be very useful to your project. Besides the
>Sram they are giving the DOS version of the development systems for free. It
>might be woth taking a look.

   Alexandre, I've looked at Atmel's 40K devices but they are expensive for
this project and the SRAM is limited to 18K. Also, I've used Lattice parts
for over two years and I'm use to their design environment. Lattice offers
Synario/ABEL HDL that supports their 44 pin devices for free. This is a very
powerful design environment. Most vendors offer Synario but it costs around
$1700. A fitter for all of Lattice's products costs an additional $1295...

>>3. 16 to 24-Bit trigger word comparator.
>
>    My main problem with trigger is that it should always allow at least two
>levels of trigering to be really useful, with just one comparison you are
>not able to trigger on more complex events.

   I could do a two-level trigger but that would require another CPLD and
I'm trying to avoid that. One thing that would be easy to add is a trigger
event counter to catch the nth occurance of a trigger. I'll look into it.
Thanks,

   - Tom

>Best regards,
>Alexandre Guimaraes
>alexg@iis.com.br