Have you taken a look at Atmel's 40k series ? They have some high speed
Sram inside the Fpga. It might be very useful to your project. Besides the
Sram they are giving the DOS version of the development systems for free. It
might be woth taking a look.

>   The following is my revised goal for this project:
>
>1. 32K storage.

    32K is fine for most applications. If you want it to trace program
execution 128K is better.

>2. 16 to 32 channels. Expandable in groups of 8.

    Again 16 is ok, 24 is fine for 8 bit micros and 32 is the ideal.

>3. 16 to 24-Bit trigger word comparator.

    My main problem with trigger is that it should always allow at least two
levels of trigering to be really useful, with just one comparison you are
not able to trigger on more complex events.

>4. 2 to 4 trigger qualifiers for signals such as *CS, *RD, *WD, *INT, etc.
>5. Internal, External, and Software clocks. Clock output.
>6. Internal 40Mhz clock with /10, /5, /4, /2, dividers. 40Msps to 1Ksps.
>7. Selectable clock polarity.
>8. 2-wire serial interface for most configuration data.

    Looks like a nice project. Please keep us informed on the project. If
you need help please fell free to ask for it.

>   If your are interested in this project, I would appreciate your
comments.
>Thanks,
>
>   - Tom

Best regards,
Alexandre Guimaraes
alexg@iis.com.br