If anyone remembers, I've been working on the hardware sections of a logic
analyzer that I intend to share. My intent is to provide a versatile
hardware design so you can write you own software for a PIC or the PC
parallel port. Originally, I wanted 40Mhz, 24 channels, 128K storage, and
DSO support. I'm trying to `squeeze' most of it into 2 Lattice ispLSI1016
CPLDs. This eliminates over 25 74X family ICs and you can get the program
software for free. The programming cable can be built for $5-$10. I supply
the object files, schematic, hardware and software documentation. I have
already released the first block, a 24-Bit trigger comparator which is
programmed via a 2-wire serial interface and supports `dont-care' Bit
states.

  Lately, I've been working on the rest of the functions which include a
17-Bit SRAM address generator, 17-Bit post-trigger counter, clock divider,
and control circuitry. I've tested the individual blocks but they will not
fit in a single 1016. I can move some of it to external `glue' logic or add
another 1016. I really don't want to do this... Note, I'm using Lattice
Synario's schematic-entry and ABEL HDL design environments.

   Since this is not a commercial product, rather something to share that
will be reasonably low-cost yet provide a versatile tool, I'm having second
thoughts on how much capability is really needed. For one thing, 128K is an
`overkill'. 32K is more than sufficient for most analyzer and DSO
applications.

   While I would like to have 24 channels, 16 is still very useful. The
number of channels mainly impact the trigger word comparator which uses a
lot of the 1016's resources. The 24-Bit version uses 90%. One option I've
considered is limiting the comparator to 16 Bits and supporting up to 32
channels expandable in groups of 8.

   The post-trigger counter is another issue. It would be easier to use a
fixed, instead of programmable, counter. One possibility is to provide a
selection of fixed-length delays such as 0, 4K, 16K, and 32K samples after
the trigger. The latter is needed for DSO applications. I need to provide at
least some options for pre- and post-trigger storage.

   The following is my revised goal for this project:

1. 32K storage.
2. 16 to 32 channels. Expandable in groups of 8.
3. 16 to 24-Bit trigger word comparator.
4. 2 to 4 trigger qualifiers for signals such as *CS, *RD, *WD, *INT, etc.
5. Internal, External, and Software clocks. Clock output.
6. Internal 40Mhz clock with /10, /5, /4, /2, dividers. 40Msps to 1Ksps.
7. Selectable clock polarity.
8. 2-wire serial interface for most configuration data.

   If your are interested in this project, I would appreciate your comments.
Thanks,

   - Tom

   A schematic for a buffered parallel port cable and programming board that
allows you to program Lattice Semiconductor's ispLSI1016, ispLSI2032, and
ispGAL22V10 devices and the ispLSI1016-based 24-Bit Trigger Word Comparator
are available from my web page at:

      http://www.teleport.com/~thandley/Wilbure.htm

   For more information about Lattice Semiconductor's products and to
download the free ISP Daisy Chain Download Programming software, contact:

      http://www.latticesemi.com