I'm sure there are lots of people on this list, including myself, who
are willing to help with your problem, but I often wonder, who
deserves the 'extra credit' ;-)

Anyway. I haven't tested this but it may help you out.

To detect a zero count, connect 2 OR gates to 193 Qa, Qb, Qc, Qd. The
outputs from these gates is connected to a NOR gate. This then gives
a logic 1 when a count of 0 is reached.

To detect a 10 count, connect an AND gate to 193 Qb and Qd. When a count
of 10 is reached a logic 1 is produced.

The output from the NOR gate and the AND gate are connected to
another OR gate and the output from this gate is connected to the
Clk input to a JK Flip Flop. The J input is tied Hi, and the K input
is tied low to toggle the FF output on positive clock pulses.

The FF Q output is connected to The Up pin on the 193.
The FF Q bar output is connected to the Dn pin on the 193.

Thus when a count of 0 or a count of 10 is reached the JK FF will
toggle and change the count state on the 193.

I just thought of this off the top of my head, so you may need to
experiment a bit. The JK FF has some extra inputs for you to connect,
but these are explained in the data sheet, and don't forget about
leaving unused gate inputs floating. Thats a no no, although TTL will
pull high if left disconnected.

Tony

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