On Fri, 13 Mar 1998 23:31:42 -0500 Frank Mckenney writes: >My first thought was that the loss of the prescaler when I re-loaded >TMR0 >was causing (mildly) erratic timing, so I descreased the prescaler >size. >down from 128 to 32. Worst I could lose would be 32 Osc/4 clocks, >right? >Well, using a five-bit prescale counter made the distortion _worse_! This type of uncertainty can be minimized by always resetting the timer at the same point in the ISR. If the timer interrupt is the only interrupt, the timer register will be zero and the prescaler a constant value (probably 3 or 4) when the first instruction in the ISR is executed. If the time delay from the interrupt to resetting the timer is always the same, then the number of cycles lost from the prescaler will also be always the same. Thus the timing will be consistent, but not necessarily exact unless a further analysis is done to make sure that the timer is written only when the prescaler is zero. _____________________________________________________________________ You don't need to buy Internet access to use free Internet e-mail. Get completely free e-mail from Juno at http://www.juno.com Or call Juno at (800) 654-JUNO [654-5866]