Morgan Olsson wrote:

> At 08:47 1998-03-12 -0800, you wrote:
> >Hi,
> >
> >For me a similarly defective devices still a beliveble ESD.
> >Just think about lightning it will goes wherever the shortest and
> >easiest discharge path goes.
>
> Naturally, Mchip must have tried to keep same protection throughout the
> device.
> Ubnless Mchip have then made a mistake, the easiest path will vary with
> process variation, and therefor should be random.
>
> >My opinion is same with ESD.
> >If  the devices has one pin which can damaged by 1000V (because
> >of the chip layout) and rest of them only will damaged by 5000V
> >my understanding is all the time the 1000V pin will destroyed.
>
> Absolutely *not* certain, unless pins are connected to same signal. (which
> is normally not done...)
>
> As long as Vdd and Vss are connected properly (or shorted together) that
> will most probably protect inner cirquitry of the chip from destruction.
> The input protection diodes vill protect until they brake down.  Ic Vdd
> and/or Vss are open. the voltage across inner cirquitry can get high so
> they get destroyed.

That is true and those devices damaged exactly because of lack of
 properhandeling.
( Kind of difficult to short Vcc and Vdd every time when you
program the chip and run to the unit to place in and make sure it is working
especially if your boss is behind you and kindly remind you this project was
due two weeks ago.)
/Peter

>
>
> So, an unconnected device can get damaged randomly (because of process
> variation) anywhere when handled unproperly.
> /Morgan

I desaggree on that one, if process would be so different we could not design
anythingunless measure every pieces and make sure what their parameters are.
The latest silicon processig technology is so good they manufacturing millions
 of
pieces with a very low fallout and if you measured them they are pretty well the
same.
But I was talking about the layout inside of the chip, on the silicon. As you
 know
they have  wires,
jumpers, gates .... processed from silicon. My understanding is, this layout has
weeknesses
as a usual layout has. If they have to wire to close or sharp corners... the ESD
going to
strike there, because looking for the easiest path to discharge.
I had MOS-Fet transistor ESD damage picture taken with electron microscope
and clearly shows ESD was strike where the gate insulation was the weakest.

/Peter

> >Altough I never did any tests in that matter, chips are to expensive
> >for that kind of game. Easier to follow some safety precaution.
> >Since I follow some basic rules I do not have any bad device.
> >
> >Peter
> >
> >Caisson wrote:
> >
> >> > Van: Peter Schultz <schupet@dvp.com>
> >> > Aan: PICLIST@MITVMA.MIT.EDU
> >> > Onderwerp: Re: Un-erasable memory in a 16C74A
> >> > Datum: donderdag 12 maart 1998 0:36
> >> >
> >> > Hi
> >> >
> >> > It is definetely not the PicStart+.
> >> > It caused by ESD damage.
> >>
> >> It crossed my mind too, but ESD could not explain the fact that _TWO_ Pic's
> >> developed an equal problem at the (for me) same moment.
> >>
> >> Oh, before I forget to mention it, I've programmed 16C77 Pic's with the
> >> same
> >> PicStart+ and all things went O.K.  No problems.
> >>
> >> So, I can cancel-out ESD damage to my Pic's and PicStart+ (unless its
> >> intermittent ofcourse).
> >>
> >> > Altough so many people in the PicList does not believe
> >> > ESD can cause that type of damage.
> >>
> >> Once fried a C64 disk-drive controller because of it, just when I remedied
> >> the
> >> problem it had.  Was not funny.  But a great example of ESD and
> >> unforgettable.
> >>
> >> > Peter
> >> >
> >> Greetz,
> >>   Rudy Wieser
> >
> >
> /  Morgan Olsson, MORGANS REGLERTEKNIK, SE-277 35 KIVIK, Sweden \
> \  mrt@iname.com, ph: +46 (0)414 70741; fax +46 (0)414 70331    /