At 09:28 1998-03-11 -0500, Robert Nansel wrote:
>Forgive me if this has been discussed before, but I've been wondering for
>some time if there are viable ways to erase OTP PIC parts. I've heard
>discussion of X-Raying and prolonged baking in the past (here and from
>other lists), but none of them sound really practical or efficacious.
>
>My idea is this: has anybody considered exposing an OTP PICs to a steep
>E-field gradient? This is essentially what happens within EEPROM devices.
>Of course the gate oxide structure for EEPROMs is different from the
>structure EPROMs, but perhaps the same effect could be induced by clamping
>an OTP package between the plates of a capacitor with a suitable voltage
>ramp profile applied to those plates. With a high enough gradient it should
>be possible to get those trapped electrons to tunnel back where they came
>from.
>
>Since I'm not an expert on semiconductor physics, these are my specific
>questions:
>
>1) Would this E-field do other, undesirable things (i.e., cause metal
>migration, oxide breakdown, etc.)?

I think not.  There will probaly be several instances of current flowing
the wron way across PN structures, but I think not so high tahat they brake
down.
That is, unless there is a electric breakdown through the encapsulation,
then there is lightning down in the chip...

>2) Would you want to ground all of the pins or tie them to the more
>positive plate? Leave them floating? Some combination?

Tie all pins to GND to ground the whole chip, and the HV pulse plate on top
of IC.  Probably the voltage nees to be so high that we nees to put the IC
and plate in a cup of silicone oil not to have discharge between plate and
pins.

>3) Since you would perforce be impressing the erase voltage gradient over
>the much larger thickness of the device package, a much larger voltage
>overall would be needed. Would the required voltage even below the
>dielectric breakdown characteristics of the package materials?

As the oxide layer in the memory cell probably withstand higher voltage per
thickness unit, will then the encapsulaiton brake down before memory is
erased?
Probably hte problem is here.
But there are maybe some concentration effects?
Probaply too, but which wins?

>4) Related to 3) above, presumably the thinner the device package, the
>steeper the E-field gradient you could get. Would this make the surface
>mount devices easier to erase? Or just easier to destroy?

More the latter, I think.  Especially the distance fron cip-to-pin
connecting wires to package surface is shorter on SMD IC.

>5) How does the voltage profile affect electron tunneling, in general?
>Would you want a gradually increasing voltage across the plates or wallop
>it with a "short, sharp shock"?

Short, sharp in order to suppres effects of leaking currents and have less
degradationof encapsulation.

>--RLN

Another question is how to make sure we are not writing cells instead of
erasing them...
1) They are easier (less energy) to reset than set them
2) Thke care to use correct polarity; - or + sharp ramp?

Methods of generating high voltage and ramp:

1) Cheap and strong: Piezo-electric igniter from cigarette lighter.
Probaly need R and/or C to lower it... and/or a gap between two conductors
to limit peak voltage.

2) Discharge tube igniting transformer and SCR etc?


Anybody dare to try?  8)

/Morgan
/  Morgan Olsson, MORGANS REGLERTEKNIK, SE-277 35 KIVIK, Sweden \
\  mrt@iname.com, ph: +46 (0)414 70741; fax +46 (0)414 70331    /