Forgive me if this has been discussed before, but I've been wondering for
some time if there are viable ways to erase OTP PIC parts. I've heard
discussion of X-Raying and prolonged baking in the past (here and from
other lists), but none of them sound really practical or efficacious.

My idea is this: has anybody considered exposing an OTP PICs to a steep
E-field gradient? This is essentially what happens within EEPROM devices.
Of course the gate oxide structure for EEPROMs is different from the
structure EPROMs, but perhaps the same effect could be induced by clamping
an OTP package between the plates of a capacitor with a suitable voltage
ramp profile applied to those plates. With a high enough gradient it should
be possible to get those trapped electrons to tunnel back where they came
from.

Since I'm not an expert on semiconductor physics, these are my specific
questions:

1) Would this E-field do other, undesirable things (i.e., cause metal
migration, oxide breakdown, etc.)?

2) Would you want to ground all of the pins or tie them to the more
positive plate? Leave them floating? Some combination?

3) Since you would perforce be impressing the erase voltage gradient over
the much larger thickness of the device package, a much larger voltage
overall would be needed. Would the required voltage even below the
dielectric breakdown characteristics of the package materials?

4) Related to 3) above, presumably the thinner the device package, the
steeper the E-field gradient you could get. Would this make the surface
mount devices easier to erase? Or just easier to destroy?

5) How does the voltage profile affect electron tunneling, in general?
Would you want a gradually increasing voltage across the plates or wallop
it with a "short, sharp shock"?

--RLN