> >We used the '77 in a project and actually had a 40 byte buffer locatated on >page 3 of RAM, so we made extensive use of indirect addressing on page 3. >We never ran into any problems. There are only 2 minor bugaboos, however >they are detailed in the data book, so there shouldn't be a problem. They >are reiterated below for convenience-sake. > >David Brobst >General Partner, Solutions Cubed Hi David, Thanks for the confirmation, Some details haven't yet been clarified, but generally the problem manifests itself in the following way. When IRP bit is set for INDF access to page 3 BUT the RP1 bit is set for page0. Everything appears fine UNTIL you perform some operation which updates the status reg. Like something which updates Z. Then everything falls over. The answer (I think) is simply to ensure the RP1 bit and the IRP bit always track each other when using INDF addressing. RP0 is of course irrelevant since the FSR is 8 bits. I should be able to confirm that this was the cause within the next few days. Ray Gardiner (DSP Systems) ray@dsp-systems.com http://www.dsp-systems.com private email to:- ray@netspace.net.au