On Tue, 3 Mar 1998, Mike Keitz wrote: > On Tue, 3 Mar 1998 17:20:00 +0100 Morgan Olsson writes: > >1) For real high speed sequential access: substitute the adress > >latches > >with loadable counters. And glue logic that advances it at every RE > >or WE > >pulse (or use separate pin). Then you have very high speed for > >sequential > >read or write. > PTM: If you have a project somewhat critical of pins, you could do like this: pic PA0 |-----res--| counter PA1 |-----up---| PA2 |--R/W-- |_______________________ | | | |||||| | | A0 A1..A15 | | | |||||| | -----------|-------- |||||| | | | |||||| PB0 |--D0/D4-----| 2x4bit |--D0/D4--| PB1 |--D1/D5-----| tri-state |--D1/D5--| SRAM PB2 |--D2/D6-----| buffer |--D2/D6--| PB3 |--D3/D7-----| |--D3/D7--| You write and read the data hinible + lonyble. Counter gives you A0 to select HI, LO. If you don't understand this picture, it is not for you, I'm not going to explain it. It works, I have used this kind of system before connected to LPT-port of a PC. If you find it usefull and use it, send me a emeil ! -------------------------------------------------------------------------- PTM, pasi.mustalahti@utu.fi, ptmusta@utu.fi, http://www.utu.fi/~ptmusta Lab.ins. (mikrotuki) ATK-keskus/Mat.Luon.Tdk OH1HEK Lab.engineer (PC support) Computer Center OI7234 Mail: Turun Yliopisto / Fysla, Vesilinnantie 5, 20014 Pt 02-3336669, FAX 02-3335632 (Pk 02-2387010, NMT 049-555577) --------------------------------------------------------------------------