Morgan Olsson wrote:

>>    Morgan, consider the proverbial stray cosmic ray, some RF
>>    noise coupling to MCLR, mains interference causing a tran-
>>    sient dip on the power rails, back EMF from a relay being
>>    switched...
>
> Yes, but TRIS register is not more sensitive than other SFR's or
> even RAM. Right?

    This depends upon the topology of the chip.  In general I
    would expect the TRIS registers to be noticeably more sensitive
    to glitches than other SFR's and RAM.

    The direction control latch would normally be part of the
    I/O 'macrocell' of each pin.  Note that there is no TRIS
    _register_ as such; there are a collection of latches dis-
    tributed around the perimeter of the chip which happen to
    be collectively addressable.

    These latches are adjacent to, and part of, the I/O pin
    circuit.  It is these circuits that carry the largest
    current flows in most systems, and which are the first
    port of call for any interference entering the chip.

>>    There are many ways in which the operation of an embedded
>>    microcontroller can be disrupted.  When it happens, it is
>>    often the I/O pin control registers that are effected.
>
> The port registers, but hardly the TRIS as they only control enable
> signals to the output drivers.

    As above, I think this distinction between the port latch
    and the direction control latch is misplaced.  Both latches
    are usually co-located on the chip and subject to very similar
    operating conditions.

___Bob