Darryl Newberry wrote:

> Also, be sure to  issue an EOI command (0x20, non-specific end of
> interrupt) to the PIC at the entry point of your ISR, otherwise you
> will lock up the machine quicker than you can say "ignore all
> interrupts".

  Well then, this isn't off topic, as it involves PICs!

  No really, my concern here was whether it is a good idea to EOI at the
START of the ISR, because you haven't released the IRQ line yet!  I
would suggest anytime after you have done the initial service on the
interrupting device, OR if I recall correctly, you mask off the IRQ in
question in the IER.

  This is an interesting point, but it appears all good IRQ code, having
initialised the appropriate bit in the IER in the start-up routine,
masks it off again each time the interrupt is serviced and re-enables it
again at the end (AFTER the EOI).  An EOI however must precede a master
Interrupt Enable for the purpose of re-entrancy of higher priority
interrupts.

  From the original:
>> The code also sets the ISR vectors
>> and a special enable bit which is called USR2 that is a final
>> interlock which can turn off the interrupts from a serial port.

  Well, that is very nice, but the IRQ gate controlled by USR2 is
usually missing in later-model single-chip I/O implementations, which
usually can't share IRQs even with properly written code.

  Cheers,
        Paul B.