Keith, I designed a Lattice ispLSI1016-based chip that implements
common microprocessor signals and a 19 Bit address bus. It connects
to PC bidirectional parallel ports where the control register, bit 5,
controls the direction. It does require an external 74xx245 bus
transceiver. I've used it for a variety of projects from interfacing A/Ds
to loading a Dallas 512K NVSRAM/Clock with math tables for my PIC-based
weather station. I intend to put it up on my `seriously in need of update'
web page soon. The following is a `snippet' from the spec:

   - Tom

----------
Generates:

  !CS ---------- !CS Chip Select
  !RD ---------- !RD Read Data
  !WD ---------- !WD Write Data
   DIR --------- Data Direction for External Bus Buffer. 1 = Read (R/W)
   HBEN -------- High Byte Enable
   A0 -> A18 --- 19 Bit Address

States:

  State   S2 S1 S0   Action
  -----------------------------------------------------------
      0    0  0  0   !RD    Generates !CS             DIR = 1
      1    0  0  1   !WD    Generates !CS             DIR = 0
      2    0  1  0   LE0    A0  -> A7  Latch Enable   DIR = 0
      3    0  1  1   LE1    A8  -> A15 Latch Enable   DIR = 0
      4    1  0  0   LE2    A16 -> A18 Latch Enable   DIR = 0
      5    1  0  1   HBEN   Latches HBEN from D0      DIR = 0

PC Parallel Port, FPGA Input/Output Interface:

  DB25         FPGA            PC Control             FPGA Outputs
  ---------------------------------------             ---------------
   1 STRB     *14 SEL IN  3    !C0                    !CS   25 I/O  8
   2 D0        15 D0  I/O 0                           !RD   26 I/O  9
   3 D1        16 D1  I/O 1                           !WD   27 I/O 10
   4 D2        17 D2  I/O 2                            DIR  28 I/O 11
   5 D3        18 D3  I/O 3                            HBEN 29 I/O 12
   6 D4        19 D4  I/O 4                            A0   10 I/O 31
   7 D5        20 D5  I/O 5                            A1    9 I/O 30
   8 D6        21 D6  I/O 6                            A2    8 I/O 29
   9 D7        22 D7  I/O 7                            A3    7 I/O 28
  14 AutoFd   *24 S0  IN  0    !C1                     A4    6 I/O 27
  16 Init     *36 S1  IN  1     C2                     A5    5 I/O 26
  17 Select   * 2 S2  IN  2    !C3                     A6    4 I/O 25
  18 GND                                               A7    3 I/O 24
                                                       A8   44 I/O 23
* pDS Router assigned these Pins                       A9   43 I/O 22
                                                       A10  42 I/O 21
                                                       A11  41 I/O 20
                                                       A12  40 I/O 19
                                                       A13  39 I/O 18
FPGA Power:                                            A14  38 I/O 17
                                                       A15  37 I/O 16
   1,23 GND                                            A16  32 I/O 15
  12,34 Vcc                                            A17  31 I/O 14
                                                       A18  30 I/O 13

At 01:10 PM 1/16/98 +0000, you wrote:
[snip]
>Try the Lattice chips. They're meant to be in-site programmable,
>so they have to be quite open about programming so that people
>can get their production jigs to program them.
>
>Why not make a general-purpose parallel I/O port and PSU outlet.
>With a standard connector like the Arcom Control Systems
>signal conditioning bus connector (50-way IDC). Or opto-22.
>
>Then you'd have a far more useful gadget which you could make
>separate plug-in boards for:
>- GAL programming
>- EPROM programming
>- Flash ROM programming
>- I2C bus EEPROMs
>- Smart cards
>- PIC chips
>- any thing you have yet to think of.
>You'd also be able to use any of Arcom's off-the shelf
>signal conditioning boards for opto-isolated switching of mains,
>relays, etc. Why re-invent the wheel?
>
>TTFN, KH
>
>