Brian Schousek writes:
>
> Note 4: After a conversion has completed, a
> 2.0 TAD delay must complete before
> acquisition can begin again. During this
> time the holding capacitor is not con-nected
> to the selected A/D input channel.
>
> What clock frequency are you running this device at? I see in your original
> post that you are using Tosc32 as your divider so a 4 MHz clock would yield
> (from table 13-1) a TAD of 8 us. giving you an additional 16 us of time
> delay necessary between conversions. 1MHz clock gives 32 us TAD-- nasty.

I'm running at 10MHz, and the conversions are taking place at 900 us
intervals, so there is plenty of time between conversions.  I've decided to
use the ~100us sampling time, since I would just be doing a delay loop
waiting for the next serial bit anyway, the extra time is not a big deal.
This will also need to work at high temperatures, so I wanted to have the
extra time used for sampling, because the data sheet could be wrong in the
temperature coefficient too.


-----------------------------
Matt Bennett                |
mjb@hazmat.com              |
http://www.hazmat.com/~mjb/ |