> Not much.  They can do I2C slave mode, but not master mode.  And
> master (and multi-master) are the real headaches.  Note that Mchip
> has put out some new PICs that supposedly support master and
> multi-master mode (16c726 or something like that) in the hardware.

Master mode is the easiest by far, especially if you restrict yourself to
EEPROM chips that don't implement the entire protocol (some I2C chips use
clock-based flow control, but I've never seen an EEPROM that did) and if
your chip is the only master on the bus.  Multi-master is probably the
hardest, because you always need to be aware of what's happening on the
bus even when it doesn't directly concern you.  This latter part makes
multi-master systems essentially impossible without hardware assistance
since the only difference between a "1" data bit and a "stop" is the order
in which the clock and data wires change state (and they may happen within
a microsecond of each other!).  Even if the bus appears idle (both wires
high) you can't know if it really is unless you saw the data-wire state on
the last rising edge of clock.  Fortunately, the I2C PICs have a circuit
for just that purpose; I don't know whether they handle all the tricky det-
ails just right, but it should be possible to do multi-master I2C on them.

Personally, I find myself sometimes wondering why I2C is so popular?  It
would seem that for the common case where a single micro hooks up to a small
number of devices over a short distance other protocols could be simpler and
faster (and cheaper--no I2C $$royalties$$).  What I'd like to see I think
would be a memory chip which could use the PIC's CLKOUT wire along with one
data pin; the data rate could then be set for CLKOUT (for PIC's with special
hardware for that purpose) or CLKOUT/12 (for PIC's without such hardware).
To make 8x51 fans happy, a CLKOUT/36 mode could also be added.  Anyone ever
heard of such a beast?