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> Fr: Mike Keitz <mkeitz@JUNO.COM>

> This is necessary, because an interrupt could occur at the start of  the
> instruction that clears GIE (while GIE is still set).  Since the
> instruction has already started, the processor finishes it, clearing GIE.
>  Then the hardware clears GIE again and goes to the ISR.  At the end of
> the ISR, the RETFIE instruction sets GIE again.  The program continues at
> the instruction following the one that was supposed to clear GIE, but GIE
> is still set.  The official way is to check GIE and clear it again if it
> ends up set.  Blindly clearing GIE twice could work too, as long as "back
> to back" interrupts can't occur.

But what happened if the interrupt (frome another source, for example)
occur during ISR?
I think two instructions clearing GIE couldn't work in this case.