In message <199712301922.NAA20751@Mars.mcs.net>, John Payson writes > >How does this relate to the portB interrupt-on-sleep function? When the >device is sleeping there aren't any clocks; is a seperate mechanism used >to handle that, or how does it work? A very good question, and one I hadn't considered. For the record, the diagram I am looking at is labelled: Fig 5.4: Block diagram of the RB7:RB4 pins for the PIC16C62A/63/64A/65A The XOR gate which detects the pin change is driven from the outputs of 2 latches, driven from Q1 and Q3. The latches appear to be transparent rather than edge clocked, so I can only assume that the clock (Q1) to the latch which monitors the actual port pin goes high during sleep. Then any pin change will pass through the latch to the XOR, generating an interrupt? It looks like Blighty is in for foul weather this weekend, so I'll try to set up an empirical test of all this RB change stuff and report back. Did anyone have a view on my other question, regarding the need to check after disabling global interrupts? -- Alan Hall, Ipswich, UK (01473) 652301