Hi,

No, the only int enable in intcon reg. is t0ie and of course gie. The rest ..
off. The stack level in ISR is 6 level deep. The reset pin is tied high and
coupled to gnd thru caps of 10nF as well as 1nF. The power source is a 12V
battery thru regu. 7805.

Any other suggesstions PLS?

Thank you

Sam
MSE

Peter Homann wrote:

> Sam S Man wrote:
>
> > Happy New Year every body!
> >
> > I'm working on a project which uses F84. There's no physical int set
> > (rb0, rb4-7). I only have tmr0 int for every 5mS and wdt is off. The
> > program reset by itself after a few int serviced. I don't understand why
> > this can happen. Can anyone help help me out on this pls?
> >
> > Thank you
> >
> > Sam
> > MSE
>
> Hi Sam,
>
> If your writing to the internal EEROM, there may be an interrupt being
> generated at the
> completion of the write cycle.
>
> I found this problem using the CCS C compiler and had to add a few assembler
> lines to clear the EEPROM interrupt flag.
>
> Does anybody know how this interrupt is meant to be handled by the CCS
> compiler, as there is no #define to identify this interrupt handler?
>
> I hope this helps.
>
> Peter.
> --
> Peter Homann   email: peterh@adacel.com.au       Work : +61 3 9596-2991
> Adacel Technologies Ltd                          Fax  : +61 3 9596-2960
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