> If you look at the data book you will see 2 versions of the port B
> circuitry, the original being an asynchronous design, where you can see
> how the problem would arise, and the Mark II which uses 2 latches,
> clocked on different internal states. It seems to me this avoids the
> problem since these is now no vulnerable period where the port pin can
> change without setting RBIF. Maybe I should set up a rig to settle this
> once and for all?

How does this relate to the portB interrupt-on-sleep function?  When the
device is sleeping there aren't any clocks; is a seperate mechanism used
to handle that, or how does it work?

My preference (except that it wouldn't be compatible with existing parts)
would be to have the portB pins compared to the OUTPUT latches.  This would
save circuitry and eliminate many of the problems related to PORTB interrupts.
Unfortunately, I don't know how to do that without breaking some existing
designs.