At 13:39 17.12.1997 +0000, you wrote:

Hi,

>I was right, there is no way I'd have got it working with the data sheets.

Oh YES ...

>Essentially, the problems is caused by the R/W bit.
>It isn't valid all the time!
>Only when the address byte arrives.

Really ?

>After that, it contains a record of the ACK bit from a data byte transfer.
>
>So if you service SSP interrupts by testing SSPSTAT R/W bit first, you're
> stuffed.
>
>The way to kludge round it is to test the Address/Data flag.
>
>        If (an incoming address)
>        {
>                if( R/W bit says Read )
>                {
>                        // received the read-address
>                        set a COPY of the R/W bit
>                        load the SSPBUF with first data byte for master
>                }
>                else
>                {
>                        // received the write-address
>                        clear a COPY of the R/W bit
>                        empty the SSPBUF to clear the BF flag
>                }
>        }
>        else
>                if( the COPY of R/W bit says Read )
>                {
>                        // received the read-data
>                        load the SSPBUF to send a byte to the master
>                }
>                else
>                {
>                        // received the write-data
>                        empty the SSPBUF to accept a byte from the master
>                        // this will clear the BF flag
>                        handling this incoming data as necessary
>                }
>        }
>

What do you think of this piece of code (16C72):

I2C     bcf     PIR1,SSPIF      ; Clear SSP Interrupt
        bsf     STATUS,RP0      ; switch to Bank1

        btfss   SSPSTAT,DA_     ; If Address were received last
        goto    access          ;  decode next access
        btfsc   SSPSTAT,RW_     ; Data were received
        goto    rd_dat          ; master has read data
        goto    wr_dat          ; master wrote data

access  btfsc   SSPSTAT,RW_     ;
        goto    rd_adr          ; master read access will follow
        goto    wr_adr          ; master write access will follow

rd_dat  bcf     STATUS,RP0      ; switch to Bank0
        movf    TXCHECK,W       ; load Checksum
        movwf   SSPBUF          ;  in I2C-Register
        bsf     SSPCON,CKP      ; enable serial clock
        goto    intout          ; data was read by master

wr_dat  bcf     STATUS,RP0      ; switch to Bank0
        movf    SSPBUF,W        ; Get I2C data
        movwf   RXBUF           ;  store it in RXBUF
        bsf     PS,I2CDATA      ; set I2CDATA Flag
        goto    intout          ; data was written, result is stored in RXBUF

rd_adr  bcf     STATUS,RP0      ; switch to Bank0
        movf    TXDATA,W        ; load DATA
        movwf   SSPBUF          ;  in I2C-Register
        bsf     SSPCON,CKP      ; enable serial clock
        goto    intout          ; data will be read by master

wr_adr  bcf     STATUS,RP0      ; switch to Bank0
        movf    SSPBUF,W        ; read SSPBUF in order to clear BF
        goto    intout          ; data will be written by master

intout  return

It seems to be working fine. Without the copy of the RW-Bit.

Any comments ?

Regards

Thomas
=8-)

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