Andrew Mayo wrote:

> I have also been pondering this. I have a circuit for a motor speed
> controller which uses an IGBT as the controlling device.

  November issue, "Silicon Chip" magazine (Australasian) I presume?

> This is PWM-switched at 1.2KHz. It switches DC, but of course, there's
> an old trick which works well if you don't mind having a control
> circuit for which the 'ground' side is not neutral.

 This is *never* the case for mains control equipment.  The magazines
have in the past published circuits switching the neutral, but have been
"advised" about it by the safety authorities.

> Place the IGBT or power MOSFET across the plus and minus side of a
> bridge rectifier. The AC side of the bridge connects in series to the
> load. The switching element always sees DC but the lamp then sees AC.

  Perfectly functional - as long as you use isolation.

> Using PWM you could make a very fine lamp dimmer - no 'hop on' or
> flicker at low brightness levels unlike triac dimmers,

  Are you referring to Triac dimmers as a breed, or to dirt-cheap
architrave-mounted domestic dimmers?  It should be obvious, but what
performance you get depends not on the switching device, but the effort
(and component count) you put into the design.

> but the 1.2KHz switching speed might be a problem for EMI - does
> anyone know how to design an effective line filter for this - would
> the same series choke design as used for a Triac dimmer work well?.

  As well as it does for the Triac dimmer.

  To be truthful, I haven't finished my dimmers, I got as far as
building two boxes each with a MOC3010 (I think) driving each of two
Triacs, and a standard opto-coupler set up to sense zero-crossings.
This was some twelve or more years ago!  The intention was to develop
the theory on a computer (of some kind) then embed it and build some
more.  I may have allowed for a transformer in one box too.  PICs are
now cheap enough to put one in each box and interface with a serial
command line.

  For a "domestic" or amateur theatre application, two channels per box
seems about right.  For more channels one needs to have a three-phase
(don't know how this applies to the US) input which should be available
in any suitable venue.

  The problem(s) with the architrave dimmer is (are) that it is quite
susceptible to line noise affecting its "zero-crossing" detection, and
being in series with the load it is reliant on the nature of the load to
detect the zero crossing.  You can do the PIC-based design just as
crudely by waiting for the zero crossing to start a timer, then
triggering each Triac as the count matches the corresponding trigger
point value.

  This can be done quite nicely with isosynchronous code performing the
actual counting if you do not need to perform other processing, or using
(again, isosynchronous) state machines for the other tasks.  It will
however be just as susceptible to power surges and ripple control
(Zellweger) tones.  What is wanted is a PLL algorithm.

  Let's see.  A PIC running a 4MHz crystal will be clocking at 1MHz.
Consider the 16C84 which has interrupts.  Let's say we use the timer
interrupt so the important thing is that the timer also clocks at 1MHz.
It "rolls over" every 256us and that is what you would presumably use
as a timer "tick" though you can of course do that faster with greater
complexity, or use the prescaler to slow it down.  Now, your half-cycle
of mains takes 8.333ms which encompasses 32.552 of these "ticks".

  The question is whether 32 equal time steps is sufficient resolution
for your dimming algorithm.  My bet is that it IS.  To avoid false
triggering, you wish to avoid the first and last, perhaps first two and
last two of these "slots".  It might also be a good idea to work in the
approximate 0.5 "tick" remainder in this counting scheme by using a
different base count on alternate interrupts, though this could
generate a minor DC offset.

  This then would be the basis for the PLL.  Once synchronised, you
count (half-) cycles of 32.5 timer overflow "ticks".  On the first and
last count, you look for the polarity change of the mains waveform and
according to whether it is late or early, accumulate an "error" count
which if it becomes larger than a given positive OR negative value such
as 10 or 20, increments or decrements the main count and is reset to a
"bias" value (not necessarily zero!).

  On each "tick", the current count is compared to the trigger index
(number from 2 to 30) and if it matches of course, the Triac is
triggered at that time and of course, the trigger device is turned OFF
on the following "tick" and has another 31 ticks at least for its
reservoir to recharge if using a capacitive series dropper for supply
voltage.

  You can of course use another algorithm to obtain initial phase
locking, during which time triggering would presumably be inhibited.
The simplest is to wait for a transition (in the desired direction) and
start the PLL at that point.  I can think of others, but that is
probably adequate.

  I presume you have thought of "soft-on" algorithms whereby the
trigger point may only be advanced by one "slot" every second or third
"tick", at least if it is currently in the last 10 or so "slots".

  Is this any use to you?

  Cheers,
        Paul B.