Mike Keitz wrote:

>
> A simple PLL will generally keep the absolute frequency
> OK, i.e. the number of processor clocks over a long
> time will be as expected.  In order for this test to
> fail the counters would have to miscount, or the
> thing come out of lock entirely.  But it is harder
> to keep the instantaneous frequency in control.

Mike is right about the long term accuracy it is just fine.
The generated clocks in some implementations behave
very similar to a PWM being used for a D/A. If you
are using execution cycles or timers driven by the
PLL clock to time an event then the results with this
type of clock can have significant jitter.

One of the reasons besides power savings by slowing down the
execution is significantly reduced EMI by controlling
computing power by demand.

Even power savings can be spectacular. I have an old
Sharp handheld PC clone that has a CMOS 8088 processor
in it. The clock speed changes based on
processing demand from 200K to 10Mhz. I don't know
exactly what algothrim it is using to control the
clock but it works. Three penlight cells will run it
continuously from Toronto to Narida (Japan) about 15 hours.


Walter Banks