On Sun, 16 Nov 1997 16:16:37 PST William Chops Westfield writes: > The proposed Microchip strategy would be VERY interesting if they > incorporate a feature that I haven't seen mentioned - that the PPL > division ratio could be PROGRAMMABLE. This way, you could change >the > clock frequency (and therefore the power consumption) on the fly. Other manufacturers do this. Another way to do it is to place a prescale counter between the crystal and the rest of the chip. This allows a low-power mode without a total shutdown. Accurate timekeeping could still be kept in the low-power mode. Most likely this isn't practical on PIC since the oscillator itself is using most of the power at high speeds anyway. >For > example, a 32768 Hz clock could be used, with a X400 division >ratio, > giving a clock of 3.2768 MHz for fast processing. For low-power >use > change the division ratio to X4 and the clock will then be 32768 Making a variable oscillator that can vary over a wide range is tricky. Probably the PIC will have a "direct from crystal" mode for lower frequencies, and a "multiplier" mode that only works for the tens of MHz range. Completely guessing in the dark, I'd say it's a fuse setting that can't be changed at run-time, since powering off and on the varaible oscillator and making a changeover might cause misclocking. This is a good idea though, since it is hard to build a 40 MHz crystal oscillator. Without completely reworking the PIC logic to single-cycle instructions (making some instructions more than 1 cycle which aren't now), this is a way to get more instructions per second. >KHz. > And you can use special division ratios to get any frequency that >is > needed - for a specific baud-rate, for example. > >Higher end Motarola "microcontrollers" (ie 68331) do this. The clock >ends >up with somewhat questionable stability, if you're using it for timing >purposes, I think. A simple PLL will generally keep the absolute frequency OK, i.e. the number of processor clocks over a long time will be as expected. In order for this test to fail the counters would have to miscount, or the thing come out of lock entirely. But it is harder to keep the instantaneous frequency in control. At least, our old 68331 based product was cursed >by or >Network Time Protocol wizards as being the only box whose timer (based >on >32768 Hz crystal) wasn't stable enough to be a credible NTP system... I thought the Motorolas had a way to route the 32 KHz crystal directly to a timer module to keep time-of-day. It's been a while since I looked at one though. If the thing isn't keeping good time at all most likely it's the 32768 crystal or oscillator that's at fault, not the multiplication. > Some may remember the 6502, which had a one microsecond >instruction > cycle when using a 1-MHz clock. It relied on nanosecond delays >inside > the chip to generate non-overlapping internal phi-1 and phi-2 >clocks. I thought it used both the clock high and clock low transitions as internal clocks. A really neat chip, well ahead of its time. If I remember, there were only a couple of cases where it would take a clock cycle that wasn't necessary to read external memory (thanks largely to it's little-ended organization). Intel managed to wrest the market away though by building a chip which had (only) what the 6502 lacked: 16-bit stack and data pointers, hooks for more than 64K memory, and vectored interrupts. The otherwise low performance of the 8086 was compensated for by massive marketing hype.