The proposed Microchip strategy would be VERY interesting if they
    incorporate a feature that I haven't seen mentioned - that the PPL
    division ratio could be PROGRAMMABLE. This way, you could change the
    clock frequency (and therefore the power consumption) on the fly. For
    example, a 32768 Hz clock could be used, with a X400 division ratio,
    giving a clock of 3.2768 MHz for fast processing. For low-power use
    change the division ratio to X4 and the clock will then be 32768 KHz.
    And you can use special division ratios to get any frequency that is
    needed - for a specific baud-rate, for example.

Higher end Motarola "microcontrollers" (ie 68331) do this.  The clock ends
up with somewhat questionable stability, if you're using it for timing
purposes, I think.  At least, our old 68331 based product was cursed by or
Network Time Protocol wizards as being the only box whose timer (based on
32768 Hz crystal) wasn't stable enough to be a credible NTP system...


    Some may remember the 6502, which had a one microsecond instruction
    cycle when using a 1-MHz clock. It relied on nanosecond delays inside
    the chip to generate non-overlapping internal phi-1 and phi-2 clocks.

Have you seen some of the research peeking its head out concerning processor
based on totally Asynchronous designs (no clock!)  Mind boggling...

BillW
cisco