Paul Britton wrote:
>I thought Intels 8751 used I/O pins for programming internal code memory
>and also they have an 'encryption array' to prevent code being read out...
>maybe Intel licenced this from Microchip, I don't know, does anyone else?

1.  Intel's "encryption array" is 64 bytes which are negated and XORed with
the data coming out:

  Data Out = Data[ Address ] ^ ( !Encrypt[ Address & 0x03F ])

Each address has a corresponding XOR value in the 64 Byte (6 address bit)
encryption array.  When the Intel part is erased, the negated encryption
array is all 0FFh which means that

  Data Out = Data[ Address ] ^ ( !Encrypt[ Address & 0x03F ])
           = Data[ Address ] ^ ( !0x0FF )
           = Data[ Address ] ^ 0x000
           = Data[ Address ]

Or no encryption takes place.

This is why Intel specifies that no data areas should be left as 0x0FF (or
even a "fill" value) if the encryption feature is used, because the
encryption value can be worked out from it.

  Data Out = Data[ Address ] ^ ( !Encrypt[ Address & 0x03F ])
           = 0x0FF ^ ( !Encrypt[ Address & 0x03F ])
Knowing that inverting a value is the same as XORing with 0x0FF:
           = 0x0FF ^ ( 0x0FF ^ Encrypt[ Address & 0x03F ])
           = 0x0FF ^ 0x0FF ^ Encrypt[ Address & 0x03F ]
           = 0 ^ Encrypt[ Address & 0x03F ]
           = Encrypt[ Address & 0x03F ]

Microchip's Code Protection/encrypting algorithm (as I understand it) is:

  Data Out = Data[ Address - 1 ] ^ Data[ Address ] ^ Data[ Address +1 ]

which works completely differently.

2.  The 8051's control store is 8 bits wide and can be read/written directly
from/to the device in parallel whereas the PIC's is 12, 14 or 16 bits and
being able to shovel in 12 or 14 bits into devices that don't have enough
I/O pins to do it in parallel is what the patent's all about.

>Just asking......Paul

No problem - it gives me a chance to repeat some stuff I just learned.  :)

myke

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