Hi,
Here is my interrupt routine, and it has not suprised me yet.
(Indeed, I have not tested it in ALL the cases.)

interrupt:
; save status
        movwf   W_TEMP          ; save W (in bank 0 or 1)
        swapf   STATUS,W                ; swapped status into W
        bcf     STATUS,RP0              ; switch to bank zero
        movwf   STATUS_TEMP             ; save STATUS
        swapf   FSR,W                   ; swapped FSR into W
        movwf   FSR_TEMP                ; save FSR
        swapf   PCLATH,W                ; swapped PCLATH into W
        movwf   PCLATH_TEMP             ; save PCLATH
        clrf    PCLATH          ; unconditionally in lowest page

; CCP1 interrupt handling
        bcf     PIR1,CCP1IF                     ; clear CCP1IF flag
        bcf     T1CON,TMR1ON            ; stop TIMER1
        movlw   HIGH ((moment0-interrupt)+3)
        movwf   TMR1H
        movlw   LOW ((moment0-interrupt)+3)
        movwf   TMR1L
        bsf     T1CON,TMR1ON            ; run TIMER1 again

moment0:

; some code (update LED par ex.)
        call    nextLED

; restore CPU
irr:
        bcf     STATUS,RP0              ; goto page 0
        swapf   PCLATH_TEMP,W   ; get swapped PCLATH into W
        movwf   PCLATH          ; restore PCLATH
        swapf   FSR_TEMP,W              ; get swapped FSR into W
        movwf   FSR                     ; restore FSR
        swapf   STATUS_TEMP,0   ; get swapped STATUS into W
        movwf   STATUS          ; restore STATUS (and reg. bank)
        swapf   W_TEMP,F                ; swap W_TEMP
        swapf   W_TEMP,W                ; swap W_TEMP into W (from anywhere save
d)

        retfie

Ivan Cenov okto7@botev.ttm.bg

----------
> From: Mike Keitz <mkeitz@JUNO.COM>
> To: PICLIST@MITVMA.MIT.EDU
> Subject: Re: Compare mode interupt, '72
> Date: 29 oKTOMWRI 1997 G. 18:02
>
> On Wed, 29 Oct 1997 00:50:32 -0500 Dave Celsnak <x93celsnak@WMICH.EDU>
> writes:
> >Just curious if any programmers can tell me if my ISR is LEGAL!
>
> Do you mean you'll get sued (and lose) for using it?  I doubt it, but I'm
> not a lawyer.  It does appear that it will work.  If you're trying to get
> exact timing, the clear of timer1 is a variable time after the interrupt.
>  This will cause inexact timing.
>
> If you go to a chip with more than 2K of program space, and use the extra
> space, you'll have to consider the possibility of interrupts occurring
> while bits 3,4, or 5 of PCLATH are set.  If that happens, the gotos in
> the ISR will go to the wrong page and the PIC will crash.