Andrew Warren wrote: > > Scott Dattalo wrote: > > > PS. Andy, I'll give you back the beer if you can score > > 4 points or buy you a bud lite if you score 3. > > Scott: > > BSF C,bit_c > BTFSS A,bit_a > BCF C,bit_c > > MOVLW 1 << bit_c ; This is legal because bit_c is a > ; literal. > > BTFSC B,bit_b > XORWF C > > Points = 9 - 6 = 3. Looks like you owe me a Bud Lite... Sure does. BTW, this is the exact complement of my solution. In other words, the BCF's are BSF's, etc. And then Mal Goris wrote: > You know, I deserve half of that Bud Lite because I independently came > up with the same solution as Andy (except I had the movlw instruction > first). You can keep my half cold and fizzy till I have a chance to > come to the States. Sorry Mal, the early worm gets the Bud. But if it's that important, I'll save the other 5 for you. Then Eric Smith, Dmitry, and Tony Nixon sent me (presumably unintentionally) their solutions. TONY NIXON, taking into account the unwise single-letter variable names, wrote: > > Assuming W reg has bit number of C before call is made > > bcf Cee,bitc > btfsc Bee,bitb > bsf Cee,bitc > > btfsc Aye,bita > xorwf Cee Well, replace the assumption with a MOVLW 1< > Hello Scott ! You act like a terrorist ;) Oh yeah, I forgot to mention Dmitry, if you don't have the fastest solution that I'm going to shoot you. > > My solution is: > > BCF C,C_BIT > MOVLW C_BIT_MASK ;C_BIT position in C > > BTFSC A,A_BIT > XORWF C,F > BTFSC B,B_BIT > XORWF C,F A variation of the theme. And finally, Eric Smith wrote: > > Scott Dattalo wrote: > > > PS. Andy, I'll give you back the beer if you can score > > 4 points or buy you a bud lite if you score 3. > > Is that offer open to others? You can have what Mal can't stand to finish. > If the bit positions of the three variables must be assumed to be different, > I think six cycles (three points) is optimal. > > I have: > > movf C,W > btfsc A,bit_a > xorlw 1< btfsc B,bit_b > xorlw 1< movwf C > > or > > clrw > btfsc A,bit_a > xorlw 1< btfsc B,bit_b > xorlw 1< xorwf C Now to add to John's alternative solutions, here's one more that's slow and stringy, but has some otherwise interesting features: BTFSC A,bit_a goto A_is_set BTFSC B,bit_b goto set_n_exit goto $+1 clear BCF C,bit_c goto exit ;Or RETURN A_is_set BTFSC B goto clear set_n_exit NOP BSF C,bit_c goto $+1 ;Or RETURN exit Features: 1) Doesn't modify W or the flags 2) Isosynchronous at 9 cycles 3) Glitch free- register C is accessed only once 4) The new state of bit_c is changed at the same relative point on all passes. This is useful for phase sensitive operations like a software PLL for example. Scott