I am pondering a predicament.  I emulate with the C73 pod on a
PicMaster.  During interrupts, the W register is saved first.  In this
case, since RP0 cannot be touched, it can go high or low.  Then, when
the saved STATUS is restored at the end of the int, the W comes back out
from the same place.  BUT.  I wrote my code to go into a windowed C554.
All will fit properly, but I have a problem.  This part has only one
bank of user RAM.  Upon interrupting, I might be in the upper page, and
then my W save action will go zinging off into cyberspace.  Even if it
makes it to the lower page, upon restoring STATUS, it will definitely
read zeros when it looks in upper page.

Unfortunately, I am using FSR, which is one work around.

Double unfortunately, I cannot bracket all high bank reads with
disabling ints, as i am interrupting on real fast timing operations.

Any grand ideas?

Chris Eddy
Pioneer Microsystems, Inc.