Hi John (John Payson), in <199708230633.BAA22381@Kitten.mcs.com> on Aug 23 you
 wrote:

> Unfortunately, Ramtron's two-wire FRAM products are more succeptible than
> two-wire EEPROMs to a particular type of glitch that has caused much
> annoyance: if the clock wire starts thrashing during a the "write" part of
> a transaction, data in the device may be erased (WILL be erased if the
> clock thrashes enough times).  Given that all read operations must be
> preceded by a "write" to set the address, it's possible for this to happen
> even if no code in the processor deliberately tries to write the data in
> the chip.

Thank you for explaining the problem in such detail. I was not aware of it,
working on an FRAM implementation right now.

Another note to the topic:  Some FRAMs (24C16 for example) have a write
protection, which allows to protect the upper half of its memory.  You can
control it with one pin, so you end up with a 3-wire-comm in case you want
to protect your memory.