> - More RAM.  More RAM.  A couple of applications I'm thinking of would
> need abut 2K of RAM.  This isn't going to happen on any of the PICs (or
> AVRs for that matter) even the so-called "high-end" ones. Interface logic
> (such as address/data multiplexers) could be added to the ports for easy
> and moderately high-performance (ideally using sub instr cycle
> resolution) connection of external RAM, either SRAM or DRAM.
>
> - Really shake up the memory map.  Right now little chunks of RAM are
> here and there, and it is all paged so global data is hard to get to.
> Change the RAM banking so the first 128 locations are unbanked and a bank
> select register selects pages for the upper 128.  (Put *all* SFRs in the
> first 128 so they can be accessed directly at any time and fill the rest
> with RAM).  Access to large data structures would be much simplified by
> just slipping one bit out of FSR and into the bank register.  And the
> data that isn't part of the large structure would stay put.

Look at Microchip's future products guide.  While I'm not sure how they plan
to have 128K of linerarly-addressible code space on a part with a 16-bit
instruction word, they do claim a 4K linear data address space.

> - A chip with internal EEPROM and more than 1K of program memory.
> Hopefully this can be done in the short term.

Also listed in the future products guide.