On Sun, 10 Aug 1997 15:53:05 +0200 Kalle Pihlajasaari writes: >Hi Dreamers, > >Here is a few Ideas I have had that would allow MicroChip to forge >ahead in the uChip field. Nothing new, just not seen them mentioned >here before. You haven't been watching very closely then. In particular, ideas about stacking W and STATUS have been discussed to death recently. >These are all ideas for getting more speed or better interrupt >response. One of the nice things about the PIC interrupt response compared to many other processors is that it's constant. No matter what the program is doing, the time from the interrupting event to execution of the first instruction in the ISR is always the same. This makes a lot of tricks possible. I would not want "enhancements" that take this away. >1 . Reduce the clock phases to one per instruction cycle. :-) Someone mentioned one of the "Future products" could contain a PLL clock multiplier to make the internal clock 4x the crystal clock, thus one instruction per crystal cycle. This is going to be necessary to increase the top speed of the PIC, since making crystals work much higher than 30 MHz is difficult. But the multiplier will likely increase the cost, increase the power consumption, and limit the minimum speed. Changing the core itself to run 1 instr per cycle is likely not feasible and it would certainly introduce a lot of multiple cycle instructions and other special cases that would complicate programming. > >2 . Increase all silicon speed to 35 MHz. Most of us usually use 4MHz or below and would not want to pay for 35 MHz silicon. Slow silicon can likely be made in a dirty old factory compared to an expensive new one and thus has the potential to lower the price. [...] >Obviously pin drive and such would get to be more of a problem at >35 Mips but FPGAs can do this and even the new Parallax SX Key looks >like it can do it (they just use 200 MHz silicon I think though). Slow IO pins are no problem other than tring to RMW output ports, which I consider to be bad practice anyway. I like the PIC's ability to sink *and source* 20 mA per pin. Things I'd like to see (in no particular order) - Lower the price. - More RAM. More RAM. A couple of applications I'm thinking of would need abut 2K of RAM. This isn't going to happen on any of the PICs (or AVRs for that matter) even the so-called "high-end" ones. Interface logic (such as address/data multiplexers) could be added to the ports for easy and moderately high-performance (ideally using sub instr cycle resolution) connection of external RAM, either SRAM or DRAM. - Really shake up the memory map. Right now little chunks of RAM are here and there, and it is all paged so global data is hard to get to. Change the RAM banking so the first 128 locations are unbanked and a bank select register selects pages for the upper 128. (Put *all* SFRs in the first 128 so they can be accessed directly at any time and fill the rest with RAM). Access to large data structures would be much simplified by just slipping one bit out of FSR and into the bank register. And the data that isn't part of the large structure would stay put. - Hardware UARTs, capture timers, etc. on an 18-pin or smaller chip. - A chip with internal EEPROM and more than 1K of program memory. Hopefully this can be done in the short term.