Hi Dreamers,

Here is a few Ideas I have had that would allow MicroChip to forge
ahead in the uChip field.  Nothing new, just not seen them mentioned
here before.

These are all ideas for getting more speed or better interrupt response.


1 . Reduce the clock phases to one per instruction cycle.  :-)

2 . Increase all silicon speed to 35 MHz.

3 . Widen stack to accommodate the W register

4 . Widen stack to accomodate STATUS register.

5 . Prefetch instruction at the interrupt vector
    so there is no prefetch required on an interrupt context
    switch going in.

6 . Widen stack to store instruction that was prefetched
    and usually discarded so return places correct instruction
    in pipeline.  This would also mean regular returns would
    be single cycle instruction as they would have the next
    instruction already available.

7 . Double the stack depth to 16 to allow compilers more freedom.

The fists 6 points above would reduce the interrupt latency from
9 cycles at 5 Mips to 2 cycles at 35 Mips.

An incease of Interrupt response of 31.5 TIMES for very minimal
changes to the core and no foundermental code compatibility
issues, could add a bit to turn on fast interrupt mode if required.

Obviously pin drive and such would get to be more of a problem at
35 Mips but FPGAs can do this and even the new Parallax SX Key looks
like it can do it (they just use 200 MHz silicon I think though).

Any comments, those from Microchip always welcome :->

Cheers
--
Kalle Pihlajasaari   kalle@ip.co.za   http://www.ip.co.za/ip
Interface Products   P O Box 15775, DOORNFONTEIN, 2028, South Africa
+ 27 (11) 402-7750   Fax: 402-7751    http://www.ip.co.za/people/kalle

DonTronics, Silicon Studio and Wirz Electronics uP Product Dealer