Walter Markiw <Walter Markiw <PICLIST@MITVMA.MIT.EDU>> wrote:

> How can I simulate a WDT overflow reset with MPLAB ?.I select
> options/developement mode/mplab simulator & 16c84 then
> options/processor setup/hardware/wdt chip reset enable but when I
> simulate a simple program such as the following,the tmr0 register
> keeps overflowing and no reset occurs:
>
> ;
> ;
>   LIST P=16C84,R=DEC
>   INCLUDE "PICREG.EQU"
> ;
> ;
>
> RESET   ORG     00H
>         GOTO    START
> START   CLRWDT
>         CLRF    TMR0
>         MOVLW   B'00001111'
>         OPTION
>         CLRWDT                 ; shuldn't tmr0 reg get cleared
>                                ; on each CLRWDT ?
>
>         MOVLW   B'00001001'
>         OPTION
>         CLRWDT
> LOOP    NOP
>         GOTO    LOOP           ; Shouldn'there happen a reset here
>                                ; on wdt overflow?
>         END

Walter:

TMR0 and the Watchdog Timer are NOT the same thing; "CLRWDT"
instructions do not affect the TMR0 register.

A reset WILL happen in your loop, but since you've assigned the
Prescaler to the WDT and set it for "divide-by-128" (with the
"MOVLW/OPTION" instructions), it won't happen until approximately
2.3 seconds of simulated execution time (approximately 2.3 million
instruction cycles at 4 MHz) has elapsed.

If you want to see the reset without having to wait for MPLAB-SIM to
simulate 2 million instructions, change the "MOVLW B'00001111'" to
"MOVLW B'00001000", or change the simulated clock speed to something
really slow, like 1 KHz.

-Andy

=== Andrew Warren - fastfwd@ix.netcom.com
=== Fast Forward Engineering - Vista, California
=== http://www.geocities.com/SiliconValley/2499