One reply was....

> From:           James <james@RADIXGROUP.COM>

> At 11:32 AM 6/30/97 -0400, you wrote:
> >Your description sounds like a delay line.  A digital soultion would be
> >characterized by the amount of uncertanty in the measurement of start and
> >stop time of the input pulse caused by sampling.  A PIC will be able to
> >sample at 1/4 the crystal rate; an 8 MHz PIC could resolve the pulse's
> >start and end to within 500 ns.
> >
> >One could first consider the non-PIC solution of a long shift register
> >which merely shifts the sampled pulse through.  To get performance
> >equivalent to the proposed PIC implementation it would require a shift
> >register of 300 stages clocked at 2 MHz.  Such registers used to be
> >available in CMOS but are probably specialized items now.
>
> Why not use a CPLD or FPGA?
> James
>

Can I get one in an 18 PIN DIP package ???

Nino Benci.
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