Mike Smith wrote:
>
> I think you're agreeing with me, somewhat.  Microchip are hamstringing
> themselves with all of this backward compatibility stuff.  They would
> do better dropping it (Shock!)  and coming out with one that
> eliminates bank-switching, uses a contiguous flat area of RAM, and
> allows a really efficient compiler to work.  While they're at it,
> how about a conventionally accessible stack pointer, another useful
> thing for compilers.

I have been part of both commercial instruction set design and
and compiler development projects. Every processor has goals and
implementation is a balancing act between many objectives. Not to
put down the Mike's comments but there is a  down side (the up side
is obvious) to your suggestions as well. A flat RAM address space
implies a bigger RAM address space and to maintain a single instruction
size that implies a wider instruction word. This is
something Microchip has already done twice with the PIC processors.
The larger silicon area costs more porportional to the square of
the die size.

We have found the value of stack frames in embedded systems
to be limited. One of our studies has shown that even a well
implemented stack frame only rarily improves performance over
a well implimented code generator. RAM usage will be essentially
identical. Here again instruction set size becomes a factor, this
time it is opcode space.

Walter Banks
http://www.bytercraft.com