> How do I prevent this?

  Well, the long and the short of it is that either you run all modules
>from the same power line (what the I2C bus was intended for = intRA-system
communications rather than intER-system), or you supply a FET switch with
gate connected to your local power rail, source to PIC and drain to the
bus.  One for each line, SDA and SCL.  Enhancement mode N-FETs of course.

> If you want, it's very easy to test it ...

  I believe you!  The problem is entirely predictable; many CMOS devices,
presumably including the PICs, have protection diodes from each input to
each rail, so by applying voltage to any input, you are trying to power
the device up via the input.  This is of course regarded as undesirable!

  Some CMOS devices such as the 4049 and 4050 and possibly their HCMOS
equivalents have only a diode (zener) to ground protecting the inputs and
can thus be operated(!) with zero supply voltage, and open-collector
outputs will likewise behave as you would desire.  Totem-pole outputs may, 
or may not.

  Of course, the difficulty is that the PIC is TOO general-putpose, and
has both input and output components hanging off each pin.

  OK, there«s my "two bits"!

  Paul B.