>> To avoid the off-topic, have you seen the new 17C5X family member?
>> 16K-word ROM, 33MHZ, "Elec. products" says it'll be priced at 13.98 for
>> thousands, prod. starting on June.

Oops, I should have said $13.28.

John Payson wrote:

>[1] A reasonable-sized area which is common to all memory banks.
>[2] Seperate bank-select bits for direct and indirect access.
>Maybe I'm being too negative since I haven't even seen the parts yet, but
>bank switching with such huge blocks is really a pain and I think there's
>no good reason for it.  IMHO, Microchip should have placed the banked-vs-
>unbanked boundary at $80; having the page chunks be 128 bytes would be no
>less convenient than having them be 224 bytes as they are now, but then
>the common area would be large enough to keep most programs' scalar
>variables.

I think it may be more convenient to have bigger pages, as it is
done now. If your program needs more than one page of RAM you can divide
it so as to keep the code of different pages connected as scarcely as
possible. Smaller pages would mean more divisions and more bank
switching. I understand you're saying that the pages are too big to even
think of this, but on the other hand I guess about 100 bytes may not be
enough, and if your using this chip instead of a cheaper one you
might have lots of code. My point is that I don't find bank-switching that
problematic and I'd consider the trade-offs. But I agree with you on the
separate bank bits, I wonder if there's a reason (maybe at the
circuit-level) for not doing it that way.

Peter F. Klammer wrote:

> MICROCHIP, ARE YOU LISTENING!!?
> ``The salient features of Extended Indirect Mode are:
> 1. Full upward compatibility with existing PIC17C4X binary code.
> 2. Single-cycle access to contiguous linearly-addressable RAM via
> indirect addressing.
> 3. Single-cycle any-bank-to-any-bank RAM copy (MOV INDR0,INDR1).
> 4. A bank-selectable 224-byte RAM context (1Ch through FFh in any bank).''

But the implementation of this seems (to me, just an observer) far from
trivial at the circuit-level. You would need a new bus for the FSRs'
higher bits, the FSRs would need added circuitry apart from doubling their
size, and you would have to add a new MUX before the register address
latch.

If I was microchip I think I'd rather use my resources to do diverse
faster and cheaper micros with more memory and peripherals, instead of
doing all this work just to save some programmers' work and perhaps make a
certain kind of code run a little faster. After all, isn't that the way
they're products are positioned? The simplicity of the scheme (from a
hardware point of view) might be one of various things that allow the high
speed and low price we expect from a PIC.

> If you want to do any kind of
> inter-bank processing, with some data in RAM bank 0 and some in RAM bank
> 1, guess how many bytes of program variables you can have for your
> sophisticated algorithm?  JUST SIX BYTES (less the one to save BSR, less
> any other interrupt saves, etc.).

I don't use 17CXX yet but I'm sure you can use banked registers too! Can't
you do something like:

        MOVPF   BSR,unbanked
        MOVLB   ISRbank
        .... use all the registers you need
        MOVLB   anotherBank    or     MOVPF W,BSR
        .... access another bank
        MOVLB   ISRbank
        .... go on, close a loop, etc                    ?

Regards,

Andres Djordjalian
adjordj@aleph.fi.uba.ar