> To avoid the off-topic, have you seen the new 17C5X family member?
> 16K-word ROM, 33MHZ, "Elec. products" says it'll be priced at 13.98 for
> thousands, prod. starting on June.

I've not seen them, but judging from the data sheets their memory layout
leaves a lot to be desired.  In particular, in any application that uses
interrupts there will only be *FIVE* useable general-purpose registers
which are held in common between banks [not counting the one which you'll
have to use up to save the bank register in any sort of meaningful ISR].
Why couldn't Microchip have taken a cue from the memory layout on the
16C924?  In particular:

[1] A reasonable-sized area which is common to all memory banks.
[2] Seperate bank-select bits for direct and indirect access.

Maybe I'm being too negative since I haven't even seen the parts yet, but
bank switching with such huge blocks is really a pain and I think there's
no good reason for it.  IMHO, Microchip should have placed the banked-vs-
unbanked boundary at $80; having the page chunks be 128 bytes would be no
less convenient than having them be 224 bytes as they are now, but then the
common area would be large enough to keep most programs' scalar variables.

Oh well, maybe someday...