>My problem is 'If the last data bit has been read from the eeprom and the
>ack has been sent back from the eeprom, when I want to generate my stop
>bit on the next high of the scl, what is to stop the next bit of data
>coming from the eeprom (D7) interfering with my sda line going up?  If
>the data (D7) is low, the sda line will stay low even if the master
>wishes it to go up because of the open drain.'
>
>Thanks for any help in advance,
> Brian.

    If you are READing from the eeprom, the master is supposed to generate
    ACK bits.
    Upon reception of the last bit from the eeprom, you need to generate
    a NACK followed by a STOP.

    Regards,
    Peter Tiang
    tiangcfoon@hitachi.com.my