My problem is 'If the last data bit has been read from the eeprom and the
ack has been sent back from the eeprom, when I want to generate my stop
bit on the next high of the scl, what is to stop the next bit of data
coming from the eeprom (D7) interfering with my sda line going up?  If
the data (D7) is low, the sda line will stay low even if the master
wishes it to go up because of the open drain.'

When the Master is reading the EEPROM it generates the ACKs.
When you are done reading you don't give an ACK, just a stop.
This is shown in on the 24C65 data sheet.

Chris


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