Hi everyone,
 I am having trouble understanding the way in which the stop condition is
produced from the master to the slave on a read/write to and from the
eeprom (24C65).  As I understand it, the protocol goes something like
this...

1. The sda line is an open drain/collector line and can only be pulled
down by any device (pulled up by external resistor).

2. Both lines in the steady state are high until the start bit (sda goes
low when scl is high)

3. Data then commences (addressing devices first) from D7 to D0 with an
ack in between.

4. The stop bit is produced after the last byte and ack.  sda goes from
low to high while the scl is high (Data transfer over).

My problem is 'If the last data bit has been read from the eeprom and the
ack has been sent back from the eeprom, when I want to generate my stop
bit on the next high of the scl, what is to stop the next bit of data
coming from the eeprom (D7) interfering with my sda line going up?  If
the data (D7) is low, the sda line will stay low even if the master
wishes it to go up because of the open drain.'

Thanks for any help in advance,
 Brian.