At 12:04 07/05/97 +0000, Ruben Jšnsson wrote:
>This all works fine - mostly! The problem is if I turn the power off
>and on again quickly (VDD goes down to about 2V), then sometimes the
>*TO bit is cleared at power up so the selftest routine thinks that it
>was a WDT timeout and goes into the error loop because the 4 ram
>registers are not 0x12345678.
>
>I use a Dallas DS1233, 5V reset circuit which gives a nice and clean
>300 ms reset pulse on MCLR at power up but this doesn't seem to
>help. The *TO bit is sometimes cleared anyway.
>
>I don't know how to deal with this problem, I can't just clear the
>WDT at reset because then I can't test it. Is there anybody else that
>has had similar problems and perhaps even solved them?

I recall having heard that in various other applications they had trouble
with this chip, and replacing it by the Maxim equivalent helped them. (You
say it's working fine, though -- they had trouble with it not giving a
proper reset pulse.)

I had a quick look at a data sheet and it says "u" for the /TO bit at a
"/MCLR Reset during normal operation", which probably is your case. Are you
sure you don't reset it somewhere?

Gerhard