Dear Microchip and Dear 17C4X users!

some of our designs, for in-chip encryption and rapid data transfer, are
hampered by the RAM address mapping of the PIC17C4X architecture.  For
instance, it is not possible to use a 256-byte table without bank switching,
which bloats the code and penalizes interrupt performance.

Would you please consider the advantages of a design in which a clean, flat
256- or 512-byte RAM array lies ``under'' the special-function registers,
which would be accessible via the INDF0 and INDF1 indrect registers?

A data-transfer loop exploiting the auto-increment features of the FSRs
could really scream, if we wouldn't have to test every iteration, ``Oops,
have we wrapped around to non-RAM addresses now?''

I would suggest a ``mode'' bit, in the BSR, to select compatibility in cases
where anyone still wants INDF0/1 to walk through the SFRs.

I have a complete paper with more details on this idea, in case anyone cares
to look at it more closely.  Anyone who wants to see a PIC17CXX REALLY scream!

Peter F. Klammer, Racom Systems Inc.                   PKlammer@ACM.Org
6080 Greenwood Plaza Boulevard                            (303)773-7411
Englewood, CO  80111                                  FAX:(303)771-4708