Hey Andy, has Microchip ever offered you a job. It wouldn't surprise
me if you and some others on this list know more about these devices than
the engineers who designed them.

Thanks for the help.

On pondering the problem a little more, I guess the same situation
applies if an interupt occurs when a GOTO or a CALL instruction
precedes it.

I can understand it a little more if I assume that the the interupt
occurs in the following way....

1) IRQ is generated.
2) Current instruction is completed.
3) PC is Updated to point to next instruction.
    This would equal either
        i) the address of the next inline instruction
        or an address generated from the current instruction, ie.
        ii) a computed address (ADDWF PCL)
        iii) a goto address
        iv) a call address
4) This address is pushed onto the stack
5) Jump to IRQ routine via 0004h
6) Retfie (Return) and execute from address pulled off stack.

Regards
Tony