Kalle Pihlajasaari <PICLIST@MITVMA.MIT.EDU> wrote:

> > adding to (or subtracting from) TMR0 is the best way to reload
> > it, for exactly the reason you describe.
>
> If I am not mistaken, this 'benefit' would be almost lost if you had
> other than a 1:1 prescaler as the prescaler value would be cleared
> and lost.

Kalle:

Yes and no.  It should be possible to write some clever code to
determine EXACTLY when the TMR0 register increments... Using that
code, you could reload TMR0 without losing the prescaler state.

I'm taking a lunch break anyway... Maybe I can come up with an
example.  Here:

    ; Enter this section with TMR0 between 128 and 255, inclusive,
    ; and the prescaler divide-by-ratio set to divide-by-4.

    WAITFOR0:

        BTFSC   TMR0,BIT7       ;WAIT FOR TMR0 TO OVERFLOW.
        GOTO    WAITFOR0        ;

    ; AT THIS POINT (SINCE OUR "WAITFOR0" LOOP HAS A RESOLUTION OF 3
    ; CYCLES), THE TMRO:PRESCALER REGISTERS CAN BE EQUAL TO ANY OF
    ; THE FOLLOWING COMBINATIONS:
    ;
    ;     TMRO  PRE
    ;      00    2
    ;      00    3
    ;      01    0

        BTFSS   TMR0,BIT0       ;IF TMR0 = 01, WASTE 2 CYCLES.
        GOTO    $+1             ;OTHERWISE, WASTE 3 CYCLES.

    ; AT THIS POINT, TMR0:PRE CAN ONLY BE EQUAL TO ONE OF THESE:
    ;
    ;     TMRO  PRE
    ;      01    1
    ;      01    2

        GOTO    $+1             ;WASTE TWO CYCLES.

    ; AT THIS POINT, TMR0:PRE CAN ONLY BE EQUAL TO ONE OF THESE:
    ;
    ;     TMRO  PRE
    ;      01    3
    ;      02    0

        BTFSS   TMR0,BIT1       ;IF TMR0 = 02, WASTE 2 CYCLES.
        GOTO    $+1             ;OTHERWISE, WASTE 3 CYCLES.

    ; AT THIS POINT, TMR0:PRE CAN ONLY BE EQUAL TO:
    ;
    ;     TMRO  PRE
    ;      02    2

        GOTO    $+1              ;WASTE TWO CYCLES.

    ; TMR0 ALWAYS INCREMENTS FROM 02 TO 03 RIGHT HERE.

        MOVLW   RELOAD+4         ;RELOAD TMR0.  WE NEED TO ADD 4 TO
        MOVWF   TMR0             ;THE RELOAD VALUE BECAUSE THESE TWO
                                 ;INSTRUCTIONS TAKE 2 CYCLES TO
                                 ;EXECUTE AND THERE'S AN ADDITIONAL
                                 ;2-CYCLE SYNCHRONIZATION DELAY.
                                 ;WHEN TMR0 STARTS INCREMENTING
                                 ;AGAIN, IT WILL BE AT -EXACTLY- THE
                                 ;MOMENT THAT TMRO:PRE WOULD HAVE
                                 ;ROLLED FROM 03:3 TO 04:0.

Of course, I haven't tested the above code -- I just typed it into
this message, so it may have bugs -- but you get the idea.  Similar
code can be written for any porescaler divide-by ratio.

-Andy

=== Andrew Warren - fastfwd@ix.netcom.com
=== Fast Forward Engineering - Vista, California
===
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